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| 71608 ms pc/o0503as (ot) no.7109-1/11 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 lb11826 overview the lb11826 is a three-phase brushless mo tor driver that is optimal for driving drum and paper feed motors in laser printers and plain paper copiers. this ic adopts a direct pwm drive technique for minimal power loss. flexible control of motor speed in response to an externally provided cl ock frequency (corresponding to the fg frequency) can be implemented by using the lb11826 in conjunction with the sanyo lb11825m. features ? three-phase bipolar drive (30v, 2.5v) ? direct pwm drive ? built-in low side inductive kickback absorbing diode ? speed discriminator + pll speed control ? speed locked state detection output ? built-in forward/reverse switching circuit ? full complement of built-in protection circuits, including cu rrent limiter circuit, thermal protection circuit, and motor constraint protection circuit. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max 30 v output current i o max t 500ms 2.5 a pd max1 independent ic 3 w allowable power dissipation pd max2 when infinitely large heat sink 20 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c monolithic digital ic for oa products three-phase brushless motor driver orderin g numbe r : EN7109a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lb11826 no.7109-2/11 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage range 1 v cc 9.5 to 28 v voltage output current ireg 0 to -30 ma ldn output current ild 0 to 15 ma electrical characteristics at ta = 25 c, v cc = vm = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 23 30 ma supply current 2 i cc 2 stop mode 3.5 5 ma output block output saturation voltage 1 v o sat1 i o = 1.0a, v o (sink) + (source) 2.0 2.5 v output saturation voltage 2 v o sat2 i o = 2.0a, v o (sink) + (source) 2.6 3.2 v output leakage current i o leak 100 a lower side diode forward voltage 1 vd1 id = -1.0a 1.2 1.5 v lower side diode forward voltage 2 vd2 id = -2.0a 1.5 2.0 v 5v voltage output output voltage vreg i o = -5ma 4.65 5.00 5.35 v voltage regulation vreg1 v cc = 9.5 to 28v 30 100 mv load regulation vreg2 i o = -5 to -20ma 20 100 mv hall amplifier input bias current ihb -2 -0.5 a common-mode input voltage range vicm 1.5 vreg-1.5 v hall input sensitivity 80 mvp-p hysteresis width v in 15 24 42 mv input voltage low high vslh 12 mv input voltage high low vshl -12 mv pwm oscillator circuit output h level voltage v oh (pwm) 2.5 2.8 3.1 v output l level voltage v ol (pwm) 1.2 1.5 1.8 v oscillator frequency f (pwm) c = 3900pf 18 khz amplitude v (pwm) 1.05 1.30 1.55 vp-p csd circuit operating voltage v oh (csd) 3.6 3.9 4.2 v external c charge current ichg -17 -12 -9 a operating time t (csd) c = 10 f, design target value* 3.3 s current limiter operation limiter vrf v cc -vm 0.45 0.5 0.55 v thermal shutdown operation thermal shutdown operating temperature tsd design target value* (junction temperature) 150 180 c hysteresis width tsd design target value* (junction temperature) 50 c fg amplifier input offset voltage v io (fg) -10 10 mv input bias current ib (fg) -1 1 a output h level voltage v oh (fg) ifgo = -0.2ma vreg-1.2 vreg-0.8 v output l level voltage v ol (fg) ifgo = 0.2ma 0.8 1.2 v fg input sensitivity gain 100-fold 3 mv schmitt amplitude for the next stage design target value* 100 180 250 mv operation frequency range 2 khz open-loop gain f (fg) = 2khz 45 51 db note : * these items are design target values and are not tested. continued on next page. lb11826 no.7109-3/11 continued from preceding page. ratings parameter symbol conditions min typ max unit speed discriminator output h level voltage v oh (d) ido = -0.1ma vreg-1.0 vreg-0.7 v output l level voltage v ol (d) ido = 0.1ma 0.8 1.1 v number of counts 512 pll output output h level voltage v oh (p) ipo = -0.1ma vreg-1.8 vreg-1.5 vreg-1.2 v output l level voltage v ol (p) ido = 0.1ma 1.2 1.5 1.8 v lock detection output l level voltage v ol (ld) ild = 10ma 0.15 0.5 v lock range 6.25 % integrator input bias current ib (int) -0.4 0.4 a output h level voltage v oh (int) iinto = -0.2ma vreg-1.2 vreg-0.8 v output l level voltage v ol (int) iinto = 0.2ma 0.8 1.2 v open-loop gain f (int) = 1khz 45 51 db gain width product design target value* 450 khz reference voltage design target value* -5% vreg/2 5% v clock input pin operating frequency range f osc 1mhz l level pin voltage v oscl i osc = -0.5ma 1.55 v h level pin current i osch v osc = v oscl + 0.5v 0.4 ma start/stop pin h level input voltage range v ih (s/s) 3.5 vreg v l level input voltage range v il (s/s) 0 1.5 v input open voltage v io (s/s) vreg-0.5 vreg v hysteresis width v in 0.35 0.50 0.65 v h level input current i ih (s/s) v (s/s) = vreg -10 0 10 a l level input current i il (s/s) v (s/s) = 0v -280 -210 a forward/reverse pin h level input voltage range v ih (f/r) 3.5 vreg v l level input voltage range v il (f/r) 0 1.5 v input open voltage v io (f/r) vreg-0.5 vreg v hysteresis width v in 0.35 0.50 0.65 v h level input current i ih (f/r) v (f/r) = vreg -10 0 10 a l level input current i il (f/r) v (f/r) = 0v -280 -210 a note : * these items are design target values and are not tested. lb11826 no.7109-4/11 package dimensions unit : mm (typ) 3174c pin assignment truth table source f/r= l f/r= h sink in1 in2 in3 in1 in2 in3 1 out2 out1 h l h l h l 2 out3 out1 h l l l h h 3 out3 out2 h h l l l h 4 out1 out2 l h l h l h 5 out1 out3 l h h h l l 6 out2 out3 l l h h h l the relation between the clock frequency, f clk , and the fg frequency, f fg , is given by the following equation. f fg (servo) = f clk / lb11826 no.7109-5/11 block diagram and peripheral circuits comp tsd curr lim csd circuit lock det speed discri pll pwm osc s/s f/r 1/512 xtal osc fgout vreg/2 - + - + - + fg amp vreg vref fgin - fgin + gnd1 + + out2 out3 out1 vm rf v cc v cc pwm vreg f/r xi xo clk in (lb11825mout) 5vreg bgp vref driver logic fg rst hys hall amp s/s dout int.in csd int amp int.out pout ld ld in1 h in2 h in3 gnd2 h lb11826 no.7109-6/11 pin functions pin no. pin name pin function equivalent circuit 28 1 2 out1 out2 out2 motor drive output pin. connect the schottky diode between the output - v cc . 3 gnd2 output gnd pin. 5 vm power and output current detection pins of the output. connect a low resi stance (rf) between this pin and v cc . the output current is limited to the current value set with i out = v rf /rf. 300 vm 5 1 2 28 3 v cc 4 v cc power pin (other than the output). 6 vreg stabilized power supply output pin (5v output). connect a capacitor (about 0.1 f) between this pin and gnd for stabilization. v cc 6 7 pwm pin to set the pwm oscillation frequency. connect a capacitor between this pin and gnd. this can be set to about 18khz with c = 3900pf. 7 vreg 200 2k 8 csd pin to set the operation time of motor lock protection circuit. connection of a capacitor (about 10 f) between csd and gnd can set the protection operation time of about 3.3seconds. 8 vreg 300 1k continued on next page. lb11826 no.7109-7/11 continued from preceding page. pin no. pin name pin function equivalent circuit 9 10 xi xo clock input pin, which enters the clock signal (1mhz or less) to the xi pin via resistor (about 5.1k ). keep the xo pin open. 9 10 vreg 11 intout integrating amplifier output (speed control pin). vreg pwm comparator 11 40k 12 intin integrating amplifier input pin. 12 vreg 300 13 pout pll output pin. 13 vreg 300 continued on next page. lb11826 no.7109-8/11 continued from preceding page. pin no. pin name pin function equivalent circuit 14 dout speed discriminator output. accelerate : high, decelerate : low. 14 vreg 300 15 ld speed lock detection output. l when the motor speed is within the speed lock range (6.25%). voltage resistance 30v max. 15 vreg 16 fgout fg amplifier output pin. vreg fg schmitt comparator 16 40k 17 18 fgin - fgin + fg amplifier input pin. connection of a capacitor (about 0.1 f) between fgin and gnd causes initial reset to the logic circuit. 300 fg reset 20k 20k 18 17 vreg 300 19 s/s start/stop control pin. low : 0v to 1.5v high : 3.5v to vreg h level when open. hysteresis width about 0.5v. 19 vreg 2k 22k 20 gnd1 gnd pin (other than the output). continued on next page. lb11826 no.7109-9/11 continued from preceding page. pin no. pin name pin function equivalent circuit 22 21 24 23 26 25 in1 + in1 - in2 + in2 - in3 + in3 - hall amplifier input. in + > in - is the input high state, and the reverse is the input low state. it is recommended that the hall signal has an amplitude of 100mvp-p (d ifferential) or more. connect a capacitor between the in + and in - inputs if there is noise in the hall sensor signals. 300 300 22 24 26 21 23 25 vreg 27 f/r forward/reverse control pin. low : 0v to 1.5v high : 3.5v to vreg h level when open. hysteresis width about 0.5v. 27 vreg 2k 22k lb11826 description 1. speed control circuit this ic performs speed control by using both the speed disc riminator circuit and pll circu it. the speed control circuit outputs the error signal once for every two cycles of fg (o ne fg cycle counted). the pll circuit outputs the phase error signal once for each cycle of fg. as the fg servo frequency is calculated as follows, the motor speed is set with the number of fg pulses and clock frequency. f fg (servo) = f clk /512 f clk : clock frequency this ic achieves variable speed control with ease when combined with lb11825m. 2. output drive circuit this ic employs a direct pwm drive method to minimize the power loss at output. the output tr is always saturated at on, and the motor drive force is adjusted through change of the duty at which the output is turned on. since the output pwm switching is made with the lower- side output tr, it is necessary to connect the schottky diode between out and v cc (because the through curr ent flows at an instant when the lower-side tr is turned on if the diode with a short reverse recovery time is not used). the diode between ou t and gnd is incorporated. wh en the large output current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky diode externally. 3. current limiting circuit the current limiting circuit performs limitin g with the current determined from i = v rf /rf (v rf = 0.5vtyp, rf : current detector resistance) (that is, th is circuit limits the peak current). limiting operation includes decrease in the output on-duty to suppress the current. 4. power save circuit this ic enters the power save condition to decrease the current dissipation in the stop mode. in this condition, the bias current of most of circuits is cut off. even in the power save condition, the 5 v regulator output is given. 5. reference clock this is entered from the external signal source (1mhz max) via a resistor (reference : about 5.1k ) in series with the xi pin. the xo pin is left open. input signal source levels : low-level voltage : 0 to 0.8v high-level voltage : 2.5 to 5.0v lb11826 no.7109-10/11 6. speed lock range the speed lock range is 6.25% of the constant speed. if the motor speed falls inside the lock range, the ld pin goes to ?l? (open collector output). when the motor speed falls outside the lock range, the on-duty ratio of motor drive output changes according to the speed error, causing control to keep the motor speed within the lock range. 7. pwm frequency pwm frequency is determined from the capacity c (f) of capacitor connected to the pwm pin. f pwm 1/ (14,400 c) it is recommended to keep the pwm frequency at 15k - 20khz. 8. hall input signal the hall input requires the signal input with an amplitude exceeding the hyster esis width (42mv max). considering the effect of noise, the input with the amplitude of 100mv or more is recommended. 9. f/r changeover motor rotation direction can be changed over with the f/r pin. when changing f/r while the motor is running, pay attention to following points. ? for the through current at a time of changeover, the countermeasure is taken using a circuit. however, it is necessary to prevent exceeding of the rated voltage (30v) due to rise of v cc voltage at a time of ch angeover (because the motor current returns instantaneously to the power supply). when this problem exists, increase the capacity of a capacitor between v cc and gnd. ? when the motor current exceeds the curr ent limit value after changeover, the lowe r-side tr is turned off. but, the upper-side tr enters the short-brake condition and the current determined from the motor counter electromotive voltage and coil resistance fl ows. it is necessary to prevent this curr ent from exceeding the rated current (2.5a). (f/r changeover at high motor speed is dangerous.) 10. motor lock protection circuit a motor lock protection circuit is incorporated for pr otection of ic and motor when the motor is locked. when the ld output is ?h? (unlocked) for a certain period in the start condition, the lower-side tr is turned off. this time is set with the capacity of the capacitor connected to th e csd pin. the time can be set to about 3.3 seconds with the capacity of 10 f (variance about 30%). set time (s) 0.33 c ( f) when the capacitor used has a leak current, due considera tion is necessary because it may cause error in the set time, etc. cancelling requires either the stop condition or re-applica tion of power supply (in the stop condition). when the lock protection circuit is not to be used, connect the csd pin to gnd. when the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be discharged completely and the lock protection activation time at restart becomes shorter than the set value. it is necessary to provide the stop time with an allowance while referring to the fo llowing equation. (the same applies to restart in the motor start transient condition.) stop time (ms) 15 c ( f) 11. power supply stabilization this ic has a large output current and is driven by switc hing, resulting in ready oscillation of the power line. it is therefore necessary to connect a capacitor with a sufficient capacity between the v cc pin and gnd for stabilization. when a diode is inserted in the power line to prevent brea kdown due to reverse connection of power supply, the power line is particularly readily oscillated. the larger capacity need be selected. 12. constant of integrating amplifier parts arrange the integrating amplifier external parts as near as possible to ic to protect them from noise effects. arrange them by keeping the largest possi ble distance from the motor. lb11826 ps no.7109-11/11 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. |
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